what causes this error?

[shaiko]

signal x : std_logic_vector ( 31 downto 0 ) ;
signal y : std_logic_vector ( 31 downto 0 ) ;
signal nibble: std_logic_vector ( 2 downto 0 ) ;

nibble <= x ( 30 downto 28 ) ;
y <= ( 30 downto 28 => nibble  , others => 'Z' ) ; -- compilation fails on this line

The above code fails compilation with the following error:
"Expression does not match type std_ulogic"

Why?

 

[axcdd]

Vectors aggregate is only possible in vhdl 2008. In ealier versions u can aggregate only bits.

so

 y <= ( 30 => nibble(2)  , 29 => nibble(1), 28 => nibble(0), others => 'Z' ) ;

 

[TrickyDicky]

or instead write:

y(30 downto 28) <= nibble;
y(31) <= 'Z';
y(27 downto 0) <= (others => 'Z');

 

[axcdd]

By the way is there any free vhdl enviroment that support vhdl 2008 with PSL commands ?. I know about AHDL and Questa but both are quite expensive