Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
SRAM CONTROL BLOCK
-- CLK GENERATION CIRCUIT
Internal Clocks are generated from the External CLK pulse
-- PRE-DECODER CIRCUIT
This circuits contains all the decoded address information from the
address bits. The decoded address will be then sent to the Row-Decoder
block where the decoded address will generate the Wordline for
selecting a memory cell for Read / Write based on the operation specified
-- COLUMN DECODER CIRCUIT
This circuit funtions in similar way to the pre-decoder circuit. This generates
the decoded address for columns. They form a integral part of the CONTROL
block when you have multiplexers in your design
-- CHIP SELECT BLOCK
This generates a internal Chip select signal which will enable/disable Read/Write
operation in your memory. This will make sure that power consumption during
no memory operation be reduced and saved
Apart from the above circuitry , you can have additional circuits like redundancy, powrer down, sleep mode, circuitry etc based on your design
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.