What are the different blocks in the Control blcok of an SRAM?

[swaroopa]

What are the different blocks in the Control blcok of an SRAM?
I have an idea that the predecoder is present here.But what exactly does it do?

 

[xreaver]

Re: SRAM Control Block

SRAM CONTROL BLOCK
-- CLK GENERATION CIRCUIT
Internal Clocks are generated from the External CLK pulse
-- PRE-DECODER CIRCUIT
This circuits contains all the decoded address information from the
address bits. The decoded address will be then sent to the Row-Decoder
block where the decoded address will generate the Wordline for
selecting a memory cell for Read / Write based on the operation specified
-- COLUMN DECODER CIRCUIT
This circuit funtions in similar way to the pre-decoder circuit. This generates
the decoded address for columns. They form a integral part of the CONTROL
block when you have multiplexers in your design
-- CHIP SELECT BLOCK
This generates a internal Chip select signal which will enable/disable Read/Write
operation in your memory. This will make sure that power consumption during
no memory operation be reduced and saved

Apart from the above circuitry , you can have additional circuits like redundancy, powrer down, sleep mode, circuitry etc based on your design