Dave Fontes
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hi guys, i'm facing a little problem , i cannot understand where this warning comes from
the code is the fowling
the warning is the fowlling
thanks for the help
the code is the fowling
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.set_of_data_items.all;
entity merge64to64 is
Port ( input_1items : in set_of_8items;
input_2items : in set_of_8items;
input_3items : in set_of_8items;
input_4items : in set_of_8items;
input_5items : in set_of_8items;
input_6items : in set_of_8items;
input_7items : in set_of_8items;
input_8items : in set_of_8items;
sorted : out set_of_64items);
end merge64to64;
architecture Behavioral of merge64to64 is
signal sorted1,sorted2 : set_of_32items;
signal out1_in2,out2_in3 : set_of_64items;
signal out3_in4,out4_in5 : set_of_64items;
signal out5_in6 : set_of_64items;
begin
sort32items1: entity work.merge32to32
port map(input_1items,input_2items,input_3items,input_4items,sorted1);
sort32items2: entity work.merge32to32
port map(input_5items,input_6items,input_7items,input_8items,sorted2);
stage6:
for i in 8*N/2-1 downto 0 generate
group1stage6: entity work.Comparator
port map(sorted1(i),sorted2(i),out1_in2(i),out1_in2(i+32));
check1stage6: if(i>=16) generate
group2stage6: entity work.Comparator
port map(out1_in2(i),out1_in2(i+16),out2_in3(i),out2_in3(i+16));
end generate;
check2stage6: if(i<16) generate
out2_in3(i)<=out1_in2(i);
out2_in3(i+48)<=out1_in2(i+48);
end generate;
check3stage6: if(i>=24) generate
group3stage6: entity work.Comparator
port map(out2_in3(i),out2_in3(i+8),out3_in4(i),out3_in4(i+8));
end generate;
check4stage6: if(i<24) generate
out3_in4(i)<=out2_in3(i);
out3_in4(i+40)<=out2_in3(i+40);
end generate;
check5stage6: if(i>=4 and i<8) generate
on_stage6: for j in 0 to 6 generate
group4stage5: entity work.Comparator
port map(out3_in4(j*8+i),out3_in4(j*8+i+4),out4_in5(j*8+i),out4_in5(j*8+i+4));
end generate on_stage6;
end generate;
check6stage6: if(i<4) generate
out4_in5(i)<=out3_in4(i);
out4_in5(i+60)<=out3_in4(i+60);
end generate;
--
check7stage6: if(i< 15) generate
on2_stage6: for k in 0 to 1 generate
group5stage6: entity work.Comparator
port map(out4_in5(2+i*4+k),out4_in5(2+i*4+k+2),out5_in6(2+i*4+k),out5_in6(2+i*4+k+2));
end generate on2_stage6;
end generate;
check8stage6: if(i<2) generate
out5_in6(i)<=out4_in5(i);
out5_in6(i+62)<=out4_in5(i+62);
end generate;
end generate stage6;
sorted<=out5_in6;
end behavioral;the warning is the fowlling
thanks for the help
