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you can download their demo version to have a try. You can use the demo version for quite long(maybe 3 months). With this tools you can read out the status of internal signal by the JTAG cable. It also supports plot the inported data versus time or versus each other. You can also export the data to do further analysis. So for data intensive application(like DSP) it is quite useful.
I've it working. It uses a lot of embeded memory block of your FPGA.
Registers are sampled with the global clock of the design.
I'm not sure that this tool is practical to use because it is impossible to implement in "touchy" design (high density design with few resource left).
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