Can anyone tell why the output is 1.6V higher than the input.[/quote]
The Lower PMOS transistor acts as a voltage follower. This common drain circuit is biased by a constant current source ( The Upper PMOS Transistor ). As a result, the transistor's overdrive voltage ( Vod = Vgs - Vth ) is determined by the bias current.
So, you get Vgs = constant ---> Any variations in the gate voltage should be followed by an equal variation in the source voltage. The Lower PMOS transistor also acts as a dc-level shifter ( the dc of the input signal is shifted by Vgs giving the output voltage )
So, I think the dc-shift at the o/p is due to the level-shifting action of the voltage follower...
I think also that PMOS is a good choice here because in PMOS transistors, you can connect the bulk and source junctions ( PMOS transistors are made in separate N-Wells, the rest of the chip is a P-Well for NMOS transistors. So, all NMOS transistors have the same bulk connection that should be connected to ground)
Some technologies allow NMOS bulk and source to be connected. However, ALL technologies ( so far as I know ) allow the PMOS's bulk and source junctions to be connected together
Connecting bulk and source avoids the problems resulting from Vth variations due to body effect....
Sorry for the long reply and hope it helps.....