Capacitive voltage divider

[mahmoud_Esmail]

I am simulating CDAC but you can think of it as cap. voltage divider issue , I did two simulations the first is for a very simple CAP. voltage divider [attached schematic] everything works fine after I set zero IC conditions on the caps , the output should be half the input which is verified using the a simulation [attached waveform] , the second simulation is bigger circuit [attached schematic ] but it really the equivalent of first schematic if you take the caps on the right in parallel , you would expect the output voltage to be half the input voltage as first case but some strange stuff is there [ attached waveforms] the output is changing while the input is constant to some strange values , I don't know what is problem as two schematics as equivalent . I am using unit cap. of 1p F then array of caps. is formed , the frequency of the input 1khz and rise and fall times are 1fs.

 

[FvM]

The second schematic is incomplete as it doesn't show the source of high frequent signal. Please clarify.

 

[mahmoud_Esmail]

The second schematic is incomplete as it doesn't show the source of high frequent signal. Please clarify.

It is there at the bottom left corner

 

[FvM]

It is there at the bottom left corner

No. The bottom left corner shows a simple square wave source. It can't generate the shown waveform.

 

[mahmoud_Esmail]

No. The bottom left corner shows a simple square wave source. It can't generate the shown waveform.

The last image shows the waveforms , the red one is the input which is square wave ranging from 1v to 2v , the yellow one is the ouput which not a square wavefrom which strange that why I'm asking

 

[KlausST]

Hi,

a square wave into a capacitive divider? Does it make sense?

A square wave is meant to have (almost) infinite dV/dt.
Using any capacitor this means almost infinite current at the edges.
"Infinite current" is what you don´t wan tto have.
It might look good in a simulation .. but it will not work well in a real circuit.

Klaus

 

[mahmoud_Esmail]

Hi,

a square wave into a capacitive divider? Does it make sense?

A square wave is meant to have (almost) infinite dV/dt.
Using any capacitor this means almost infinite current at the edges.
"Infinite current" is what you don´t wan tto have.
It might look good in a simulation .. but it will not work well in a real circuit.

Klaus

Well capacitive DACs are based on cap. Voltage divider concept the input are digital signals bits the ouptut is analog voltag

 

[KlausST]

Hi,

true. But they - because realistic - have meaningful rise / fall time and series resistance.

A "too idealistic simulation" may cause the "two capacitor paradox" problem ... or simply suffer from variables overflow.

Klaus

 

[FvM]

So you are claiming that simulator generates the step waveform with 16*fsquare output without introducing any switches, additional voltage sources or time-variant components? Unlikely. I guess the actual circuit is different and has controlled switches.
Is it Cadence Spectre simulator? Can you show the generated netlist?

 

[mahmoud_Esmail]

Hi,

true. But they - because realistic - have meaningful rise / fall time and series resistance.

A "too idealistic simulation" may cause the "two capacitor paradox" problem ... or simply suffer from variables overflow.

Klaus

I added a resistor at input voltage source of resistance 1 ohm nothing changed

 

[mahmoud_Esmail]

So you are claiming that simulator generates the step waveform with 16*fsquare output without introducing any switches, additional voltage sources or time-variant components? Unlikely. I guess the actual circuit is different and has controlled switches.
Is it Cadence Spectre simulator? Can you show the generated netlist?

Yes this is cadence , Okay i will share it