# voltage follower with PMOS

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#### matlabprob

##### Newbie level 3
pmos voltage follower

I have voltage follower with two PMOS transistors in series.
constant DC voltage is given to the gate of 1 transistor and input is give to the gate of other transistor and is biased with VDD(3.5V) and VSS(gnd).

When I simulated this circuit in the cadence for input Vsin(±1V AC and 1V Amplitude)

I am getting an output starting at 1.6V and following the input signal . i.e AC voltage difference is zero.

Can anyone tell why the output is 1.6V higher than the input.

##### Full Member level 6
voltage follower schematic

Could you send the schematic?

The description is not clear

#### Syukri

##### Full Member level 5
Well maybe becasue the connection of the series pMOS, pMOS sent good high logic where the Vgs is +Vth value

u got 2 pMOS means 2Vth is added to the signal...

But I think i a schematic will help to analyze ur question..

#### matlabprob

##### Newbie level 3
schematic for the sample and hold voltage follower T2 and T3

##### Full Member level 6
Can anyone tell why the output is 1.6V higher than the input.[/quote]

The Lower PMOS transistor acts as a voltage follower. This common drain circuit is biased by a constant current source ( The Upper PMOS Transistor ). As a result, the transistor's overdrive voltage ( Vod = Vgs - Vth ) is determined by the bias current.

So, you get Vgs = constant ---> Any variations in the gate voltage should be followed by an equal variation in the source voltage. The Lower PMOS transistor also acts as a dc-level shifter ( the dc of the input signal is shifted by Vgs giving the output voltage )

So, I think the dc-shift at the o/p is due to the level-shifting action of the voltage follower...

I think also that PMOS is a good choice here because in PMOS transistors, you can connect the bulk and source junctions ( PMOS transistors are made in separate N-Wells, the rest of the chip is a P-Well for NMOS transistors. So, all NMOS transistors have the same bulk connection that should be connected to ground)

Some technologies allow NMOS bulk and source to be connected. However, ALL technologies ( so far as I know ) allow the PMOS's bulk and source junctions to be connected together

Connecting bulk and source avoids the problems resulting from Vth variations due to body effect....

Sorry for the long reply and hope it helps.....

#### matlabprob

##### Newbie level 3
Thanks for the reply it helped a lot.

Also I am looking for implementation of the
above circuit using matlab RF tool box. I already implemented this in Cadence.
I want compare the same circuit in both technologies (i.e cadence and matlab).

In order to implement this using MATLAB 7.0.1 RF TOOLBOX to find frequency response in RF frequency range(GHZ range). We have to build a small signal model

Does any one know how to find appropriate small signal parameter values Cds,Cgs,Cgd ,Gds,Gm (of T1,T2,T3) for IN of say 1V,Vb1 of 2V and Vdd of 3.5 V.

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