yannik33
Member level 1
Why differentiate VLSI-Systems between active and n+ resp. p+ ? If the p+ region is larger doesn't this increase the likelihood of an short circuit between drain and source (eg in the figure below there is a connection between drain and source side doesn't this lead to a short circuit?)?
![capture002.png capture002.png](https://www.edaboard.com/data/attachments/50/50370-7ca95cb0f4676794aa71f0dddcae89d1.jpg)
(**broken link removed** ,p. 7)
![capture002.png capture002.png](https://www.edaboard.com/data/attachments/50/50370-7ca95cb0f4676794aa71f0dddcae89d1.jpg)
(**broken link removed** ,p. 7)