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VHDL/Verilog code help!!!

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sudan

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Hi everyone,

I am doing my project 'Image compression implementing in FPGA' . If anyone having VHDL or Verilog code for this (using any algorithm) Please send me to
sudan_1k89@yahoo.in

sudan
 

sudan

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Re: VHDL code doubt !!

Hi ,
It is helpful Amr. One more question...

Can we read inputs from a file ? for that any VHDL comments are present ? Please help....


Sudan
 

amraldo

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I do not get your question Sudan!!
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Amr Ali
 

sudan

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Hi Amr,

Suppose we are designing an encoder. For that we have to give input at the simulation time or real time through key board. My question is , I am having a binary data in a file. I want to encode the binary file using the encoder in the simulation automatically. Is it possible ???

Sudan
 

amraldo

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Yes it is possible, and you can read your data from an image file to your encoder and write the output into an image file again.

You will have to use the textio library.

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Amr Ali
 

sudan

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Hai Amr,


Can you give an example code for that. Please ???

Sudan
 

amraldo

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Check this post
Also you can interface verilog with any C code that does that using PLI.
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Amr Ali
 

amraldo

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Check the link above in the post.
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Amr Ali
 

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