VHDL tutorial explaining the synthesizable code

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ramspoly

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I'm looking for some tutorial which explains what syntax in VHDL is synthesizable to a particular hardware block. For example, with-select or case statement can be synthesizable to MUX and if else statement synthesizable to MUX with priorities etc.
 

ramspoly,
There are lots of things you can find by searching the net.
**broken link removed**

This is only one of them.
Hope that helps some.
Sckoarn
 

Thank you!!

---------- Post added at 05:12 ---------- Previous post was at 05:11 ----------

thank you!!
 

I have a habit that using vcom with -check_synthesis option in Modelsim. I think this great option for synthesizable code
 

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