VHDL tutorial explaining the synthesizable code

[ramspoly]

I'm looking for some tutorial which explains what syntax in VHDL is synthesizable to a particular hardware block. For example, with-select or case statement can be synthesizable to MUX and if else statement synthesizable to MUX with priorities etc.

 

[Sckoarn]

ramspoly,
There are lots of things you can find by searching the net.
**broken link removed**

This is only one of them.
Hope that helps some.
Sckoarn

 

[ckshivaram]

i think this is what you are looking for

VHDL Tutorial: Learn by Example
**broken link removed**

 

[ramspoly]

Thank you!!

---------- Post added at 05:12 ---------- Previous post was at 05:11 ----------

thank you!!

 

[alexan_e]

Also check
VHDL Synthesis Reference

VHDL reference manual

Alex

 

[dnk0904]

I have a habit that using vcom with -check_synthesis option in Modelsim. I think this great option for synthesizable code