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[SOLVED] VHDL simulation in Cadence

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granjan

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Hi ,

I just wanted to know what are the different simulation and compilation options for VHDL files...how to compile vhdl file using ncvhdl and do we need to create work library for vhdl file compilation.I'm new to vhdl.. any help is appreciated....:???::???:
 

I believe you have already read carefully the documentation?
 

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