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VHDL equivalent for Verilog readmemb ?

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deepa1206

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Hi Could anybody let me know what the VHDL equivalent of "$readmemb" (in Verilog) would be?

Thanks
 

Thank you for your reply. I want to read a .txt file and load its contents in a ROM/RAM. Can I make this procedure synthesizable?

Please let me know.
 

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