nnmate
Junior Member level 1
VHDL compiling error with "not " operator : expression is not of type IEEE BALABALA
Hi all,
by compiling a VHDL FSM file I met a serie of errors which said expression is not of type IEEE.STD_LOGIC_1164.STD_ULOGIC, direct at my not operator for a bit input signal.
the code is on the website of OSU **broken link removed**
and the error happens at
temp_pout(11) := not sin ;
temp_pout(10) := not sin ;
etc.
I have changed the type of sin into bit, std_logic or std_ulogic, but the errors are still there.
Can someone just compile that .vhd and lets discuss?
ps. my EDA is Synopsys Design Compiler in Linux.
General question: this sin signal is directly input pin/signal. Can we just use not operator on him and assign that to the outputing variable?
Hi all,
by compiling a VHDL FSM file I met a serie of errors which said expression is not of type IEEE.STD_LOGIC_1164.STD_ULOGIC, direct at my not operator for a bit input signal.
the code is on the website of OSU **broken link removed**
and the error happens at
temp_pout(11) := not sin ;
temp_pout(10) := not sin ;
etc.
I have changed the type of sin into bit, std_logic or std_ulogic, but the errors are still there.
Can someone just compile that .vhd and lets discuss?
ps. my EDA is Synopsys Design Compiler in Linux.
General question: this sin signal is directly input pin/signal. Can we just use not operator on him and assign that to the outputing variable?