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VHDL compiling error with "not " operator : expression is not of type IEEE BALABALA

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nnmate

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VHDL compiling error with "not " operator : expression is not of type IEEE BALABALA

Hi all,

by compiling a VHDL FSM file I met a serie of errors which said expression is not of type IEEE.STD_LOGIC_1164.STD_ULOGIC, direct at my not operator for a bit input signal.

the code is on the website of OSU **broken link removed**

and the error happens at

temp_pout(11) := not sin ;
temp_pout(10) := not sin ;
etc.

I have changed the type of sin into bit, std_logic or std_ulogic, but the errors are still there.

Can someone just compile that .vhd and lets discuss?

ps. my EDA is Synopsys Design Compiler in Linux.

General question: this sin signal is directly input pin/signal. Can we just use not operator on him and assign that to the outputing variable?
 

Re: VHDL compiling error with "not " operator : expression is not of type IEEE BALABA

Where are the libraries declaring the types vlbit and vlbit vector? why do these type even exist? In your posted code, you have not even included ieee.std_logic_1164.all, so you cannot even use std_ulogic.

The problem is because VHDL has strong typing, so a std_ulogic is not a bit, and a vlbit is not a std_ulogic. You have to do a type conversion to assign one to the other, and that often means writing a type conversion function. So Im guessing you havent written a custom not function that converts sin into a vlbit?

Basic answer - Dont use custom bit types. You should use standard libraries for everything.
 

Re: VHDL compiling error with "not " operator : expression is not of type IEEE BALABA

Hi Tricky,
thanks a lot for your reply.
I was not saying std_logic=bit=std_ulogic. I surely know and have used ieee.std_logic_1164.all. Then I changed the comic vlvector vlbit into std_logic_vector and std_logic, and met the errors.

I just want to know if other ppl can help me to understand the error. If not, I want to discuss it and make it workable. I think I don't need type conversion function. I just wanna guarantee synthesizable codes.
 

Re: VHDL compiling error with "not " operator : expression is not of type IEEE BALABA

in that case, please post updated code.
 

Re: VHDL compiling error with "not " operator : expression is not of type IEEE BALABA

This error is because the 'not' function is defined in the Synth libarary that is used in the code ( **broken link removed**) . If you still want to use the not function, then you need to create and compile the same synth library in your simulator. Another way is to create your own library and compile all the necessary packages, etc to that one. Then in your code.. use it as

Library <your lib>;
Use <your_lib>.all;

This will solve the problem... Why the compiler is spitting out errors for the code is because it cant find the definition of the 'not' keywork/function among the standard libraries that come with IEEE 1164 or others supplied by the tool vendor. You should take the package files that are being used for your code/design and compile them to another custom library and then use them in your code as shown above.
 

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