[SOLVED] vhdl code for cypher....i am having the problem in this code ...can anyone help me?

[chandrapal1990]

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

---- my libraries declarations ----
library CIPHER;

entity geffe is
port(
Clk :in std_logic_vector;
Rst :in std_logic;
Keystream ut std_logic
);
end geffe;

---------------------------------------------------------------------
---------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library CIPHER;

architecture geffe_structure of geffe is

---- Component declarations -----


component lfsr_13
generic(N : integer := 13);
port (
clk :in std_logic;
reset :in std_logic;
lfsr_out ut std_logic
);
end component;






component lfsr_5
generic(N : integer := 5);
port (
clk :in std_logic;
reset :in std_logic;
lfsr_out ut std_logic
);
end component;




component lfsr_8
generic(N : integer := 8);
port (
clk :in std_logic;
reset :in std_logic;
lfsr_out ut std_logic
);
end component;




component mux2_1
port (
inA :in std_logic;
inB :in std_logic;
selectline :in std_logic;
output ut std_logic
);
end component;

---- Signal declarations used on the schematic diagram ----

signal x1 :std_logic;
signal x2 :std_logic;
signal x3 :std_logic;
--signal clk :std_logic;
--signal Rst :std_logic;
--signal Keystream: std_logic;

begin

---- Component instantiations ----

LFSR_1 : lfsr_13
port map(
clk => clk,
lfsr_out => x1,
reset => Rst
);

LFSR_2 : lfsr_8
port map(
clk => Clk,
lfsr_out => x2,
reset => Rst
);

LFSR_3 : lfsr_5
port map(
clk => Clk,
lfsr_out => x3,
reset => Rst
);

Mux21 : mux2_1
port map(
inA => x1,
inB => x3,
output => Keystream,
selectline => x2
);

end geffe_structure;

 

[TrickyDicky]

you didnt say what the problems are.

 

[chandrapal1990]

it is showing library CIPHER not found....

 

[TrickyDicky]

then you need to create the cypher library in the tool you're using- but given you dont use anything from it - you dont need it.