VHDL and Verilog which one you use more often?

[maestor]

In Spain:
I know in Universities in Spain is more popular VHDL, it depends of the University of course but most of them teach VHDL.

In places like Madrid and Barcelona you can find companies using VHDL and companies using Verilog although 80% is VHDL.

I also know that in Scotland, in the Silicon Glen where I spent 3 years, there is more VHDL than Verilog but is very close, there are a lot of American companies (less these days unfortunately) there which use Verilog.

I am a VHDL guy, I have done some Verilog and what can I say I don't like it, it's too 'softy'! VHDL is easy to learn, describes hardware much better than Verilog (your bug-fix turn around should be shorter), it has things like records, configuration...which are great, specially records which give you a lot of flexibility in your code.

The only thing I've heard these days which benefits Verilog is simulation time, tools like Modelsim are X (?) times faster simulating Verilog than VHDL.

Regards,
Maestor

 

[always@smart]

Hi all,

I think more and more designer talk bout SystemC vs System Verilog...right? What are your concern?

Regards,
always@smart

 

[bellbell]

I use verilog. And my friends in Irvine, California, and friends in San Jose, California are using Verilog.

 

[Robin_zhu]

we use verilog in our company

 

[chiente]

Verilog is more popular at bayarea.
VHDL is still welcom at Japan & Europe.

VHDL is more robust on synthesis; it won't give any surprise.

Verilog has more flexibility and is powerful on TestBench, like PLI ..
but, will need formal verification between RTL & netlist. And this
give EDA company to sell more tools

 

[sxqzj]

i think chiente is right,and in china ,verilog is becoming more and more popular than VHDL!

 

[beta0]

We use the both languages in our company,althought
I use the verilog often, I am more fond of the VHDL .

 

[hgz]

verilog

 

[efundas]

I was using VHDL almost 2years back, now I am working only in verilog.

 

[ITP]

Hi efundas,

Why you have switched from VHDL to verilog?

Regards
Itp

 

[efool]

Verilog

 

[llrry]

verilog is popular in Taiwan and Korea.

 

[oasis]

verilog is popular in ASIC, and vhdl is more used in FPGA

 

[visualart]

I use verilog, It is my darling!

 

[FoxyRick]

I use both, since I'm still learning to handle CPLD's and FPGA's. I am starting to prefer Verilog, but the jury is still deciding.

I think my decision is based on the ease of use of freely available tools though, not necessarily the best tool!

Cheers,
FoxyRick.

 

[semicon]

In US, there is this misconception that Verilog is a better choice for ASIC design.

 

[amarnath]

i prefer verilog...because of its smillarity to a high level programming language like C

 

[dreeke]

Hi,

We use only VHDL (European standard was told to us)

 

[blacklancer]

In our companies in china use Verilog, but in school teach vhdl

 

[Bajaj]

most of engineer learn c in school. so verilog leaning is very easy