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In germany schools VHDL is preferred. But they teach also Verilog because the most tools use a Verilog output!
Big german companys like infineon are also using Verilog, but in military research the most using VHDL.
SystemVerilog has been stealing features from VHDL
I went to a SystemVerilog tutorial a few days ago presented by Synopsys guys. It looks like the SystemVerilog developers have been stealing features from VHDL all over the place -- configuration, multi-dimensional array, pointer, record ... You name it. Almost every nice feature VHDL has that Verilog lacks, they copy it and put it in SystemVerilog. Their purpose is very clear -- one language for both design and verification (SystemVerilog also "borrowed" features from Vera). I'm wondering what these guys are trying to do. Instead of beefing up Verilog, why don't they make their synthesis tool understand VHDL better.
In US, there is this misconception that Verilog is a better choice for ASIC design. What people don't realize is, Verilog is fairly loose while VHDL is strongly typed. Using Verilog, you gotta have a good lint tool to do the design diagnosis upfront. This is almost an extra step in the design flow. With VHDL, most errors can be found during compling. There is little effort needed to do linting. Also, Verilog is a very poor language in terms of verification. You can't even use it for verification. Then you end up buying fancy tools to do the verification -- Specman, Vera etc.. Wouldn't that complicate the whole design flow? Now a designer has to deal with several languages and several tools to just get a piece of code done.
I guess the industry always goes in a direction that maximizes the pockets of the CEOs at the EDA companies. Considering the depressed job market in US, maybe we should all start promoting Verilog -- you gotta hire more people, hire more verification consultant to get the same job done. That may be a good thing for all of us in this industry.