VGA display using fpga

[Basu_Gouda]

VGA disply using fpga

Hi

with respect to the above subject i am using a spartan 6 board to connect my acer tft display. the monitor when connected to the board is showing "input not supported" dialogue. please help me.


thanks in advance.

 

[ads-ee]

Re: VGA disply using fpga

Hi

with respect to the above subject i am using a spartan 6 board to connect my acer tft display. the monitor when connected to the board is showing "input not supported" dialogue. please help me.


thanks in advance.

Explain how someone is going to help you given this post has no useful information on your design. Do you believe everyone on edaboard can read your mind?

 

[Basu_Gouda]

Re: VGA disply using fpga

Explain how someone is going to help you given this post has no useful information on your design. Do you believe everyone on edaboard can read your mind?

The design is for the Spartan XC6SLX9 using 100MHz clock frequency and a display of 640*480 pixels. The clk has been divided for 25MHz and used for the construction. The module is prepared with the guidance of " FPGA prototyping using verilog " book. Once debugged and implemented the monitor is not supporting the video.

The sync code is as follows

---

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module vga_sync(pixel_x,pixel_y,hsync,vsync,video_on,clk,rst);
output [9:0]pixel_x,pixel_y;//total pixels
output video_on,hsync,vsync;
input clk,rst;
 
localparam HP=640;
localparam VP=480;
localparam VR=2;
localparam HR=96;
localparam HFP=48;
localparam VTP=33;
localparam HBP=16;
localparam VBP=10;
 
 
reg [9:0]hcount_reg,vcount_reg,hcount_temp,vcount_temp;
wire hsync_temp,vsync_temp;
reg hsync_reg,vsync_reg;
 
wire hend,vend,pixel_tick;
 
 
always@(posedge clk)
    begin
    if(rst)
    begin 
    hcount_reg<=0;
    vcount_reg<=0;
    hsync_reg<=1'b0;
    vsync_reg<=1'b0;
    end
    else
    begin
    hcount_reg<=hcount_temp;
    vcount_reg<=vcount_temp;
    hsync_reg<=hsync_temp;
    vsync_reg<=vsync_temp;
    end
    end
    
    assign hend=(hcount_reg==(HP+HFP+HBP+HR-1));
    assign  vend=(vcount_reg==(VP+VTP+VBP+VR-1));
    
    always@(posedge clk)
    begin
    if(hend)
    hcount_temp=0;
    else
    hcount_temp=hcount_reg+1'b1;
    end
    /*always@*
    begin
    if(posedge clk)
    if(hend)hcount_temp=0;else hcount_temp=hcount_reg+1;
    else
    hcount_temp=hcount_reg;
    end
    */
    
    always@(posedge clk) 
    begin
    if(hend)
    if(vend)
    vcount_temp=0;
    else
    vcount_temp=vcount_reg+1'b1;
    else
    vcount_temp=vcount_reg;
    end
    
    assign hsync_temp=(hcount_reg>=(HP+HBP)&& hcount_reg<=(HP+HBP+HR-1));
    assign vsync_temp=(vcount_reg>=(VP+VBP)&& hcount_reg<=(VP+VBP+VR-1));
    
    
    assign video_on=(hcount_reg<HP)&&(vcount_reg<VP);
    
//output
    assign hsync=hsync_reg;
    assign vsync=vsync_reg;
    assign pixel_x=hcount_reg;
    assign pixel_y=vcount_reg;
    
endmodule

---

 

[matrixofdynamism]

Re: VGA disply using fpga

Well, having experienced this before, what happened in my case was that I did not have the correct timing for synchronization signals i.e the HSYNC and VSYNC were not occuring at correct times.

Please note that if you are not outputting data such the digital display can mark the top left and bottom left edge of the frame. It may not show correct display. OK, lets make this more clear. I wrote a pong game in which the screen was all black but the bar and ball were white. When I did simulation it should that the bars were 30 pixels away from the screen edges. When I actally put the design onto the FPGA and connected it to my LCD, there was no space between screen edge and the bars. Thus. when I added a white frame of 1 pixel line width, it worked correctly. But that is my experience and observation and opinion.

 

[Warpspeed]

Re: VGA disply using fpga

There are a huge number of different VGA signal standards, more than most people realise, and here is a list of just some of them :

http://tinyvga.com/vga-timing

So you plug some magic "VGA" compatible video box into your monitor, and your monitor, measures the incoming signal up to decide which VGA standard it is being fed with.
It goes through a long list in an internal library and cannot identify the incoming signal as corresponding with anything it can recognise in its internal list of VGA standards.

So its just telling you whatever you are sending it is not supported.

So you get the error message.
Not much you can really do about it either.