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FPGA PR error message

Fun-King

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Message display as fellow. Is there any suggestion?

[Place 30-99] Placer failed with error: 'Design cannot be split into multiple SLRs due to overutilization: 106.7% LUT utilization in SLR2, 82505 SLLs required between SLR2 and SLR3 of 23040 SLLs available.


Resolution: Review and adjust physical constraints including use of Pblocks, PROHIBIT, USER_SLR_ASSIGNMENT, and USER_CROSSING_SLR that may affect the ability to partition the design into SLRs.'

Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.
 

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The error is self explanatory, you are using too many Shift Register Lookup cells in the device or region that you are using for implementing the circuit.

It appears you may be using a Xilinx part as that error is a placer error from their tools.

As @FvM says "Any information about design structure and purpose?" because that is the only way we can help suggest ways to fix the problem.
 

Fun-King

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FPGA type? Tool? Any information about design structure and purpose?
VU19P
PR tool: Vivado
--- Updated ---

The error is self explanatory, you are using too many Shift Register Lookup cells in the device or region that you are using for implementing the circuit.

It appears you may be using a Xilinx part as that error is a placer error from their tools.

As @FvM says "Any information about design structure and purpose?" because that is the only way we can help suggest ways to fix the problem.
VU19P
PR tool: Vivado

Is this means: fix from front-end is the best way to solve this problem ?
Is there some suggestion to solve this error from PR tool or synthesis tool ?
 

dpaul

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@Fun-King
Is this means: fix from front-end is the best way to solve this problem ?
Yes.

If I were you, I would go through the RTL and try to optimize the design such that it uses less resources.
Seems like a huge design as you have run out of resources on a VU device!
 

Fun-King

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@Fun-King

Yes.

If I were you, I would go through the RTL and try to optimize the design such that it uses less resources.
Seems like a huge design as you have run out of resources on a VU device!
Thanks for your suggestion, I will have a try.
 

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