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i have also used saed90nm library provided by synopsys but this pdk are not realistic its is only for learn tool .
its for learning tool and for small design.
you must have to use standard pdk like UMC, TSMC, SCL etc.
there is nothing wrong with using SAED library. this is not why OP is seeing a huge delay.
if you add input/output delay constrain file (.sdc) or added input/output delay "attribute "then this problem may came.
remove all attributive then simulate and check results after that.