Hi, im trying to synthesize the openMSP40 processor using design compiler, using the saed90nm library, can anyone tell me why im getting this very large delay on the AND gate.. thanks!
i have also used saed90nm library provided by synopsys but this pdk are not realistic its is only for learn tool .
its for learning tool and for small design.
you must have to use standard pdk like UMC, TSMC, SCL etc.
i have also used saed90nm library provided by synopsys but this pdk are not realistic its is only for learn tool .
its for learning tool and for small design.
you must have to use standard pdk like UMC, TSMC, SCL etc.
if you add input/output delay constrain file (.sdc) or added input/output delay "attribute "then this problem may came.
remove all attributive then simulate and check results after that.
if you add input/output delay constrain file (.sdc) or added input/output delay "attribute "then this problem may came.
remove all attributive then simulate and check results after that.
That is not the case, input delays would not show up as delay of the output of a std cell. Check the screenshot again. It is very likely a huge load, maybe a reset signal like pointed out in replies #2 and #3.