verlog code for 4 bit parallel adder

[divsec]

i want verilog test bench code for 4 bit parallel adder?how to write it/

 

[ckaa]

you could use this as a starting point. There maybe minor errors in the framework below:

module adder_tb();
reg clk, reset;
reg [3:0] a,b;
reg carry_in;
wire carry_out;

//adjust your delay according to your reset pulse width
initial begin
clk = 0;
reset = 0;
#20 reset = 1;
#20 reset = 0;

//Insert your stimulus for a,b and carry in here.
//I have just put in an example below
a = 4'b1100;
b = 4'b1011;
carry_in = 1'b1;

#450
a= 4'b1110;
b = 4'b0010;
carry_in = 1'b0;
end

//determine your clock period and adjust the delay below
always #50 clk = ~clk;

//Instantiate your parallel adder here. Example shown below:
adder adder_inst(
.rst(reset),
.clk(clk),
.A(a),
.B(b),
.carry_in(carry_in),
.carry_out(carry_out)
);

endmodule