verilogs question ans it?

[abhineet22]

1.What is the difference between Behavior modeling and RTL modeling?
2.What is the benefit of using Behavior modeling style over RTL modeling?
3.What is the difference between blocking assignments and non-blocking assignments ?
4.How do you implement the bi-directional ports in Verilog HDL
5.How to model inertial and transport delay using Verilog?
6.How to synchronize control signals and data between two different clock domains?

 

[wkong_zhu]

1) behavior verilog is to verify the circuit function. and RTL is to describe the real circuit.
in behavior verilog, you can use all the language that simulator supports, such as force, release, wait, disable, etc. But RTL verilog only can use that the synthesizer supports.

 

[no_mad]

Hi abhineet,

Please check out this weblink by rajesh:
https://www.angelfire.com/in/verilogfaq/techqa.html#How to model Transport and Inertial Delays in

enjoy

 

[zysmith]

behaviour code is more readable and is written with high abstract, simulation speed is faster to reduce run time, it need'nt is synthesized.

 

[YUV]

1.What is the difference between Behavior modeling and RTL modeling?
2.What is the benefit of using Behavior modeling style over RTL modeling?
3.What is the difference between blocking assignments and non-blocking assignments ?
4.How do you implement the bi-directional ports in Verilog HDL
5.How to model inertial and transport delay using Verilog?
6.How to synchronize control signals and data between two different clock domains?

1), 2) I think, zysmith has already answered.
3) Example: you have 3 triggers a, b, c.
Blocking assignment acts immediately (during a clock event):
a=in;
b=a;
c=b;
This is equivalent c=in. After synthesis you will see 3 parallel triggers. Even more - changing of order of lines will lead to different results.
Non-blocking assignment occures after the clock event.
a<=in;
b<=a;
c<=b;
In this case input value will reach output after 3 clocks. Order of lines might be any.
4) It must be used "inout" statement. Output must be 3-stable
assign out = enable ? in : 1'bz; // for 1 bit bus
5) ---
6) Usually, FIFO is used in that situation. Also, a metastability factor should be taken in account. You have asked a complex question. It's impossible to give a simple answer.

 

[spauls]

you can read
Verilog by Samir Palnitkar,
all your doubts will be cleared ,
it is in EDA foroum

 

[JesseKing]

I think you should read a verilog book carefully first.

 

[feel_on_on]

u ought to study verilog carefully .so many question !

 

[zhangpengyu]

RTL is register transition level,is fsm + datapath.
Behavior modeling is high than RTL .

 

[eeeraghu]

These are the basic q's as of starting verilog. If u refer to any verilog book or tutorial these are basics in verilog.

 

[srik_naidu]

hi,
consider in initial block blocking statements are executed sequentially while nonblocking statements will executed in parallel.
with non blocking statements you can also face racing condition.


with regards,
srik

 

[manik_vivek_82]

Hi,
As far as Q2 is considered, synthesis time as well as synthesisability is better with RTL coding style.
Vivek

 

[soccer]

1.the behavior modeling can be a transaction level disign, but the RTL modeling is more close to real logic circuit.
2.for behavior verification in the early time of design.
3. any textbook on hdl can explain it.
4.using bi-directional ports in Verilog HDL
5.add #? in your program.
6.using a register.