Verilog tool simulation for transistor level

[Jim85]

I am looking for a free tool (or even for a trial version) which is able to simulate verilog code at transistor level .


Is anyone who can suggest me any tool ?

 

[tariq786]

All tools like cadence incisive, synopsys vcs, mentor graphics modelsim support transistor (switch level primitives) as defined in verilog standard. See those primitives here

https://www.asic-world.com/verilog/gate1.html

 

[Jim85]

Yes but don't forget but i am looking for a free tool or a trial version. cadence,synopsys,modelsim is not free tool!

Have you any other ideas ?

 

[tariq786]

you should look at icarus verilog

google is your friend

 

[Jim85]

With this (icarus verilog) would i have the ability to see the schematic or is just for compiling ?

 

[tariq786]

why not you read the documentation?

 

[Jim85]

tariq786 i tried the icarus but i didn't see that is able to create the schematic of the circuit. Do you know that can do it ?? (if yes please explain me how ?)

or if you mean that i can see the schematic via modelsim please explain me how .


Thank in advance.