verilog spartan 3E 2nd line of LCD display isnot showing data

[Hafeez Ur Rehman]

I am facing a problem in my LCD interface code..
Is there any other reason for not getting data on 2nd line of LCD!!!???
Hoping for the help and guidance....




here is my lcd_mod module

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Code Verilog - [expand]
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module lcd_mod
  (
   input  CLK_50MHZ,
   output LCD_E,
   output LCD_RS,
   output LCD_RW,
   output [3:0] LCD_D,
 
 
  // input  [31:0] if_data,
   input         if_write,
   output        if_ready
   );
  reg  [127:0] if_data=128'h56539856123455221234567812345678;
//  always @ (posedge clk)
  
  reg [7:0]  disp_data;
  reg        disp_rs;
  reg [31:0] disp_delay;
  reg        disp_write;
  wire       disp_ready;
  reg        disp_b8;
  
  reg [7:0]  char;
  reg [1:0]  state;
  reg [127:0] number;
  reg        init_done;
  reg        running;
  reg [5:0]  shift_cntr;
  
  reg        if_ready_r;
  assign if_ready = if_ready_r;
 
 
  
  lcd_display display
    (.clk(CLK_50MHZ),
     .rst(1'b0),
 
 
     .lcd_e(LCD_E),
     .lcd_rw(LCD_RW),
     .lcd_rs(LCD_RS),
     .lcd_d(LCD_D),
 
 
     .if_data(disp_data),   // hafeez?
     .if_rs(disp_rs),
     .if_delay(disp_delay),
     .if_write(disp_write),
     .if_ready(disp_ready),
     .if_8bit(disp_b8)
     );
 
 
  
  
  parameter NB_CHARS     = 8'd12;
  
  parameter START        = 2'b00,
            WAIT_WRITE_0 = 2'b01,
            WRITE_1      = 2'b10,
            WAIT_WRITE_1 = 2'b11;
 
 
 
 
  initial begin
    state <= 2'b00;
    char <= 8'b0;
    init_done <= 1'b0;
    if_ready_r <= 1'b0;
    shift_cntr <= 5'b0;
  end
 
 
  
  always@ (posedge CLK_50MHZ) begin
    if (init_done && char > 8'd26) begin//najam
      if (disp_ready)
        if_ready_r <= 1'b1;
      if (if_write) begin
        char <= 4'd8;          // reset the display
      end
    end else if (char <= 8'd26) begin//najam
      if_ready_r <= 1'b0;
      
      case (state)
        START:
          if (disp_ready) begin
            disp_write <= 1'b1;
            state <= WAIT_WRITE_0;
          end
        
        WAIT_WRITE_0:
          state <= WRITE_1;
        
        WRITE_1:
          begin
            disp_write <= 1'b0;
            state <= 2'b11;
          end
        
        WAIT_WRITE_1:
          begin
            state <= START;
            char <= char + 8'b1;
          end 
      endcase // case (state)
    end // else: !if(!running)
  end // always@ (posedge CLK_50MHZ)
 
 
 
 
  always@ (negedge CLK_50MHZ) begin
    // these next steps initialize the LCD display:
    case (char)
      0: 
        begin 
          disp_b8 <= 1'b0;
          disp_data <= 8'h30;
          disp_delay <= 32'd10000000;
          disp_rs <= 1'b0;
        end
 
 
      1: disp_data <= 8'h30;
 
 
      2: 
        begin 
          disp_data <= 8'h30;
          disp_delay <= 32'd1000000;
        end
      
      3: 
        begin 
          disp_data <= 8'h20;
          disp_delay <= 32'd20000;
        end
      
      4: 
        begin 
          disp_b8 <= 1'b1;
          disp_data <= 8'h28;
        end
      
      5: disp_data <= 8'h06;
      
      6: disp_data <= 8'h0C;
 
 
      7: 
        begin 
          disp_data <= 8'h01;
          disp_delay <= 32'd1000000;
          init_done <= 1'b1;
          shift_cntr <= 5'd32;//najam
        end
 
 
      8: // this state provides an entry point to reset the display and then
        // go on to the default state that writes the number
        begin 
          disp_rs <= 1'b0;
          disp_data <= 8'h01;
          disp_delay <= 32'd1000000;
          shift_cntr <= 5'b0;
          number <= if_data;
        end
          
      
      default:
        // state machine to print a 32-bit number out
        if (disp_ready && state == START) begin
          if (shift_cntr < 5'd31) begin//najam
            disp_rs <= 1'b1;
            disp_delay <= 32'd10000;
            if (number[127:124] < 4'b1010)
              disp_data <= number[127:124] + 8'h30;
            else
              disp_data <= number[127:124] + 8'h37;
            number <= number << 4;
            shift_cntr <= shift_cntr + 5'b1;
                  //disp_data<= 8'h48;
          end 
        end
    endcase // case (char)  
  end // always@ (negedge CLK_50MHZ)
  
endmodule

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[bhabbott]

Hitachi 44780 based LCD modules do not automatically move the cursor from the end of line 1 to the start of line 2. The first line starts at LCD address 0x00 and goes to 0x0F (in a 16x2 display), but the second line starts at 0x40. If you just keep printing characters without repositioning the cursor then the second line will go to 0x10~0x1F and not be displayed.

You need a register to keep track of the current cursor position, incrementing it after each character is sent. When it reaches 0x10 (or any time you want to print on the second line) you should then send a 'Set DDRAM Address' instruction (0b1xxxxxxx) with the address field set to 0x40.