VERILOG RTL code help

tarek1984 · Dec 25, 2010

Hi
i want to make this
pi = pi ⊕ pi−1

so i tried to use a d-flip flop to store the pi−1 to xor it with the new pi

and i used this verilog code for it

module FDC (
D , // Data Input
C , // Clock Input
CLR , // Reset input
Q // Q output
);
//-----------Input Ports---------------
input D, C, CLR ;

//-----------Output Ports---------------
output Q;

//------------Internal Variables--------
reg Q;

//-------------Code Starts Here---------

always @ ( C )
if (~CLR) begin
Q <= 1'b0;
end else begin
Q <= D;
end

endmodule

but for some reasons this do not work well

in the beginning i give a clear pulse to the d-ff then i need it give a delayed value of the previous output .
Can any body help me by this verilog code

thanks

FvM · Dec 25, 2010

You have coded a synchronous reset for the DFF, is that what you intend?

but for some reasons this do not work well

Can you be more specific?

P.S.: I didn't see, that the always block misses an edge sensitive condition. It can't work.
A standard DFF with positive clock edge and low active clear looks like this:

Code:

always @ (posedge C or negedge CLR)
if (~CLR) begin
Q <= 1'b0;
end else begin
Q <= D;
end

VERILOG RTL code help

tarek1984

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VERILOG RTL code help

tarek1984

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