I am reading the book "Writing Testbench" and found my previous testbench style is RTL.
Can I change Verilog RTL Testbench to Behavioral Testbench, is the below code right?
In fact, these two different descriptions are not the same if the comprehension on the meaning of wait (signal_a) especially if this statement is used in post-layout simulation.
To be the same, the sampled under the rising edge of the clock shall be used as follow:
wait (signal_a_sampled);
two total different descrition, only the same if you are waiting for the occur(one time event) of the En, in this status the later one should be more efficient
i dont think verilog is a good behavioral modeling language. it's short of high-level description capability. using verilog to write rtl model is more comfort, if you want high-level modeling, turn to system verilog or system c.