Verilog RTL and Behavioral Testbench

[davyzhu]

Hi all,

I am reading the book "Writing Testbench" and found my previous testbench style is RTL.
Can I change Verilog RTL Testbench to Behavioral Testbench, is the below code right?

//---- RTL style---
Always@(posedge clk)
If(EN)
...
//------------------

//----Behavioral style---
Always begin
wait(EN)；
@(posedge clk);
...
end
//-----------------------

Is there any other better Behavioral style?

Any suggestions will be appreciated!
Best regards,
Davy

 

[muhammad kashif]

this is the write way to right programe in behavioral level

 

[Thomson]

In fact, these two different descriptions are not the same if the comprehension on the meaning of wait (signal_a) especially if this statement is used in post-layout simulation.

To be the same, the sampled under the rising edge of the clock shall be used as follow:
wait (signal_a_sampled);

Best Regards,

Thomson

 

[davyzhu]

I see.

When EN in not valid @(posedge clk), the behavioral model will be wrong. How to write a full right model?

Best regards,
Davy

 

[woodyplum]

two total different descrition, only the same if you are waiting for the occur(one time event) of the En, in this status the later one should be more efficient

 

[JesseKing]

agree with thomson.

and I want to know why you want to convert your rtl to behavioral level

 

[archillios]

i dont think verilog is a good behavioral modeling language. it's short of high-level description capability. using verilog to write rtl model is more comfort, if you want high-level modeling, turn to system verilog or system c.