xstal
Full Member level 2
verilog non synthesizable constructs
Is it synthesizable???
Thanks in advance.
Is it synthesizable???
Code:
module DELAY1 (clk,in1,out1);
input clk, in1;
output out1;
reg out1;
reg temp;
always
begin
@ (negedge clk)
temp = in1;
out1 = temp;
end
endmodule
Thanks in advance.