# Verilog: Is it synthesizable???

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#### xstal

##### Full Member level 2
verilog non synthesizable constructs

Is it synthesizable???

Code:
module DELAY1 (clk,in1,out1);
input  clk, in1;
output  out1;
reg  out1;

reg  temp;

always
begin
@ (negedge clk)
temp = in1;
out1 = temp;
end

endmodule

#### FvM

##### Super Moderator
Staff member
verilog parser site:edaboard.com

Hello,

apart from a syntax error, corrected this way
Code:
always    @(negedge clk)
begin
temp = in1;
out1 = temp;
end
this classical RTL code, defining a synchronous flip-flop. However, for the final assgnment a non-blocking statement should be used for clarification. Also the temp reg is redundant here, this would be the code's functional essential:
Code:
always    @(negedge clk)
begin
out1 <= in1;
end

For a good description of blocking/non-blocking issues see the paper below, suggested by forum member NanhTrang

Regards,
Frank

#### xstal

##### Full Member level 2
synthesizable verilog construct

Thanks frank for your promt reply. But my code does not have any syntex error. I deliberately put @(negedge clk) after begin to control the event. This is valid syntax and passes with ncverilog simulation. Your solution is a very common flop architecture.
So my original question is stand still.
Thanks.

#### FvM

##### Super Moderator
Staff member
verilog event synthesizable?

Hello,

as far as I understood, you're concluding from the fact that ncverilog accepts the following construct, that it should be valid syntax.
Code:
always
begin
@ (negedge clk)
As first point, I don't understand, what shall be it's meaning in contrast to well-known always @() syntax.

As second point, if it has a particular meaning, that I don't yet see, where is the syntax defined?

My guess is, that you see a side effect of the said Verilog compiler's parser apparently allowing begin end bracketing everywhere in text, even when no legal Verilog syntax is formed.

Regards,
Frank

P.S.: Additionally, I can tell that Quartus integrated synthesis also accepts the syntax, result is single flip-flop as with the minimal code I suggested. I still wonder, if the construct follows a general Verilog syntax rule.

#### omara007

negedge verilog

xstal said:
Thanks frank for your promt reply. But my code does not have any syntex error. I deliberately put @(negedge clk) after begin to control the event. This is valid syntax and passes with ncverilog simulation. Your solution is a very common flop architecture.
So my original question is stand still.
Thanks.

May I ask what is your original intention from this code ? .. In other words, what do you want to do (or what is your target behavior) so as you coded your circuit this way ?

#### FvM

##### Super Moderator
Staff member
the meaning of synthesizable

Hello,

I now understand the meaning of original construct, although it's somewhat unsual. It's legal Verilog code and also synthesizable, but may cause misunderstandings due to similarity with usual construct. The point is, that only the first assignment is clock synchronous, the second is combinational. In this particular case, the result is identical with the usual construct, but this must not necessarily be the case.
Code:
always
begin
@ (negedge clk)
temp = in1;  // should be written temp <= in1 for clarity
out1 = temp; // continous assignment!
end
The unusual and possibly misleading point is mixing of edge sensitive and continous assignments in an always block. It has no particular meaning, but is obviously legal Verilog syntax.

Regards,
Frank

#### xstal

##### Full Member level 2
Thanks Frank,
Others please refer Verilog HDL LRM (8.6.6 Intra-Assignment Timing Controls)

Frank, As you told that this is a synthesizable construct, can you please let me know which synthesis tool gives the intended netlist. Because I am not sure which tool can do synthesis for thiis construct.

Thanks,
xstal

#### FvM

##### Super Moderator
Staff member

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