I've started learning Verilog HDL for a while. Now, I'm studying gate level design. I wrote a module which ran normally in its test bench but when I further used it in another module something went wrong. The wrong thing is that I have a nand gate (in a module)whose inputs are {0 , 0} and its output is x. How come ?!
Thanks for your concern, imbichie . The problem was due to opposing inputs and outputs of one module. And I shall use the safe form of instantiating any module as