Verilog HDL-Gate level design

[Alaa El-Din Mohamed]

Hi

I've started learning Verilog HDL for a while. Now, I'm studying gate level design. I wrote a module which ran normally in its test bench but when I further used it in another module something went wrong. The wrong thing is that I have a nand gate (in a module)whose inputs are {0 , 0} and its output is x. How come ?!

Thanks in advance.

 

[ads-ee]

perhaps the output is connected to another driver.

 

[Alaa El-Din Mohamed]

sorry, ads-ee. I didn't get your answer. But as an information, the output of this nand gate is connected directly to another nand only.

 

[imbichie]

Can you please post your code,
That NAND output signal may be multiple driven.

 

[Alaa El-Din Mohamed]

Can you please post your code,
That NAND output signal may be multiple driven.

Thanks for your concern, imbichie . The problem was due to opposing inputs and outputs of one module. And I shall use the safe form of instantiating any module as

module ****( .o(output) , .i1(first input) ,....... )