Dec 26, 2012 #1 S Sam Cristtina Junior Member level 1 Joined May 13, 2012 Messages 15 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,380 Hi,I'm newbe in verilog using with spartan-xilinx, and want to gererates 2ns delay between two state(on or off) of i/o line. always @ (posedge clk) begin temp = 1'b1;//output wire #2; // delay. wait for 2ns temp = 1'b0;//output wire #2; // delay end This is generate delay in simulation. but when I check this output line on CRO,There is no delay. output line is continues zero. Is there any way to generate delay without use of clk?
Hi,I'm newbe in verilog using with spartan-xilinx, and want to gererates 2ns delay between two state(on or off) of i/o line. always @ (posedge clk) begin temp = 1'b1;//output wire #2; // delay. wait for 2ns temp = 1'b0;//output wire #2; // delay end This is generate delay in simulation. but when I check this output line on CRO,There is no delay. output line is continues zero. Is there any way to generate delay without use of clk?
Dec 27, 2012 #2 FvM Super Moderator Staff member Joined Jan 22, 2008 Messages 52,513 Helped 14,760 Reputation 29,802 Reaction score 14,128 Trophy points 1,393 Location Bochum, Germany Activity points 298,484 Is there any way to generate delay without use of clk? Click to expand... I guess you'll find the answer in any text book about Verilog for logic synthesis and uncountable previous threads. Clearly no.
Is there any way to generate delay without use of clk? Click to expand... I guess you'll find the answer in any text book about Verilog for logic synthesis and uncountable previous threads. Clearly no.