Sam Cristtina
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Hi,I'm newbe in verilog using with spartan-xilinx, and want to gererates 2ns delay between two state(on or off) of i/o line.
always @ (posedge clk)
begin
temp = 1'b1;//output wire
#2; // delay. wait for 2ns
temp = 1'b0;//output wire
#2; // delay
end
This is generate delay in simulation. but when I check this output line on CRO,There is no delay. output line is continues zero.
Is there any way to generate delay without use of clk?
always @ (posedge clk)
begin
temp = 1'b1;//output wire
#2; // delay. wait for 2ns
temp = 1'b0;//output wire
#2; // delay
end
This is generate delay in simulation. but when I check this output line on CRO,There is no delay. output line is continues zero.
Is there any way to generate delay without use of clk?
