testing PNP saturation threw pulse "delay" shape

[yefj]

Hello,I have attached two LTSPICE files.There are two kinds of plots,saturated and non saturated shown below.
I dont understand where is the significant delay in the signal in the saturated state.
How can i see that there is stretch in the non saturated PNP?
Saturated PNP

NON Saturated

 

[D.A.(Tony)Stewart]

Get your logic diagram to conform. Positive high.

Balance your bias and don't saturate the base.
Then prevent Vcb > Veb with a clamp diode.

 

[dick_freebird]

Models lie. Have seen many which have real delays in us
range with model TR set to ns values. Do you see any
mfr recovery time spec to validate model behavior? Or
have you ever gone and set up the bench test jigs to
do it for real, as I think was suggested?

 

[D.A.(Tony)Stewart]

Notice the improvement using negative feedback on my design.