steven852
Advanced Member level 4
Hi,
I have a mux coded in this way:
always @(*) begin
if (enable) begin
case(select)
4'b0000: ...
4'b0001: ...
4'b0010: ...
....
4'b1000: ...
endcase
end
end
Notice that the "select" only has full case for the lower 3 bits while the MSB is used only for one case. I tried to come up another mux with 3 control bits. Or something like this:
case({select[2],select[1],select[0]})
3'b000: ...
...
3'b111: ...
endcase
But what is the best coding style to handle the case when select[3]==1? Basically is it possible to avoid another mux to make the netlist simpler?
I think this solution will lower the area.
Thanks.
I have a mux coded in this way:
always @(*) begin
if (enable) begin
case(select)
4'b0000: ...
4'b0001: ...
4'b0010: ...
....
4'b1000: ...
endcase
end
end
Notice that the "select" only has full case for the lower 3 bits while the MSB is used only for one case. I tried to come up another mux with 3 control bits. Or something like this:
case({select[2],select[1],select[0]})
3'b000: ...
...
3'b111: ...
endcase
But what is the best coding style to handle the case when select[3]==1? Basically is it possible to avoid another mux to make the netlist simpler?
I think this solution will lower the area.
Thanks.