Apr 27, 2011 #1 A amarj Newbie level 4 Joined Apr 27, 2011 Messages 5 Helped 1 Reputation 2 Reaction score 0 Trophy points 1,281 Activity points 1,312 i need verilog code for 16 bit synchronous counter with synchronous hold..pls help me out..
Apr 27, 2011 #2 J jagz Newbie level 5 Joined Aug 22, 2009 Messages 10 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Location Ind Activity points 1,361 is it with synchronous reset?
Apr 27, 2011 #3 bigdogguru Administrator Joined Mar 12, 2010 Messages 9,821 Helped 2,350 Reputation 4,694 Reaction score 2,272 Trophy points 1,413 Location Southwest, USA Activity points 62,383 Have you check Altera's website: Verilog HDL: Parameterized Counter Join the Verilog HDL Group there are numerous links to free and open source cores.
Have you check Altera's website: Verilog HDL: Parameterized Counter Join the Verilog HDL Group there are numerous links to free and open source cores.
Apr 28, 2011 #4 A amarj Newbie level 4 Joined Apr 27, 2011 Messages 5 Helped 1 Reputation 2 Reaction score 0 Trophy points 1,281 Activity points 1,312 jagz said: is it with synchronous reset? Click to expand... ya...with synchronous reset and synchronous hold.. ---------- Post added at 09:13 ---------- Previous post was at 08:48 ---------- module(clk,hold,reset,q); input clk,hold,reset; output [15:0]q; reg [15:0]q; initial q=15'b0000000000000000; always @(posedge clk) begin if (reset) q=15'b0000000000000000; else if (hold) q=q; else q=q+1; end endmodule im getting the simulation correct but i need get output on fpga . Every time i apply a monopulse count its jumping from 0 to 129.. wats the prob???
jagz said: is it with synchronous reset? Click to expand... ya...with synchronous reset and synchronous hold.. ---------- Post added at 09:13 ---------- Previous post was at 08:48 ---------- module(clk,hold,reset,q); input clk,hold,reset; output [15:0]q; reg [15:0]q; initial q=15'b0000000000000000; always @(posedge clk) begin if (reset) q=15'b0000000000000000; else if (hold) q=q; else q=q+1; end endmodule im getting the simulation correct but i need get output on fpga . Every time i apply a monopulse count its jumping from 0 to 129.. wats the prob???