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verilog code for 16 bit counter

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amarj

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i need verilog code for 16 bit synchronous counter with synchronous hold..pls help me out..
 

jagz

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is it with synchronous reset?
 

amarj

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is it with synchronous reset?
ya...with synchronous reset and synchronous hold..

---------- Post added at 09:13 ---------- Previous post was at 08:48 ----------

module(clk,hold,reset,q);
input clk,hold,reset;
output [15:0]q;
reg [15:0]q;
initial q=15'b0000000000000000;
always @(posedge clk)
begin
if (reset)
q=15'b0000000000000000;
else if (hold)
q=q;
else
q=q+1;
end
endmodule

im getting the simulation correct but i need get output on fpga . Every time i apply a monopulse count its jumping from 0 to 129.. wats the prob???
 

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