The difference can easily be understood with philosophies of Verilog non-blocking and blocking statement.
In any always block <= is a non blocking one and all such statement will be executed simultaneously. After synthesis these will result in FF's.
whereas = is a blocking one in your case X = Y and Y = X will be executed sequentially and both X and Y will have Y finally. I think this is not what is intended !
The first case is ok. a is assigned to b and at the same time b is assigned to a. That means a and b could have difference values depands on the initial values.
For the second case, value of b is assigned to a and b wont change...
the second one, both a and b will have value of b.
there is a virtual-temp value for every variable, so the previous signal can be hold there until the clock edge. all assignment will take the temp value for any operation.
the temp value will get updated after clock pulse come in.