verilog code difference

[spauls]

simple verilog code

Hi All,

i have two codes for swapping of a and b , which one should be OK .

always @ (posedge clock ) begin
a <=b ;
b <= a;
end

always @ (posedge clock) begin
a =b ;
b = a;
end

please clarify.

 

[AlexWan]

vhdl code for swapping register

First one is OK.

For example:
Now, a=X, b=Y. After posedge of clock, result of first one is a=Y, b=X, and result of second one is a=Y, b=Y.

You can find some papers of blocking &non-blocking assignment of Verilog to check it.

 

[z81203]

1 second clock verilog code

first is simultaneously, second is sequentially.

 

[aravind]

verilog code for swapping

when synthesis
first non-blocking take 2 dff shifting there outputs
more reference ADVANCE VERILOG Training by Cummuings

second blocking statement will take on (dff)register give the output as b and input as a

 

[sameer_dlh25]

verilog difference = <=

Hi Spauls,

The difference can easily be understood with philosophies of Verilog non-blocking and blocking statement.

In any always block <= is a non blocking one and all such statement will be executed simultaneously. After synthesis these will result in FF's.

whereas = is a blocking one in your case X = Y and Y = X will be executed sequentially and both X and Y will have Y finally. I think this is not what is intended !

 

[jjww110]

how to profile verilog code

you should understand block and non-block in verilog!!

 

[phoenixfeng]

difference assignment <= and = in verilog

I agree with sameer_dlh25 and AlexWan

 

[spauls]

can anybody suggests good book on verilog starting from scratch

 

[aravind]

HDL chip design by Doulas smith
Verilog HDL by samir palnikar
Verilog Synthesis by Baskar

this 3 books must for all Verilog beginers

 

[weng]

The first case is ok. a is assigned to b and at the same time b is assigned to a. That means a and b could have difference values depands on the initial values.

For the second case, value of b is assigned to a and b wont change...

 

[yuenkit]

first one.

the second one, both a and b will have value of b.

there is a virtual-temp value for every variable, so the previous signal can be hold there until the clock edge. all assignment will take the temp value for any operation.

the temp value will get updated after clock pulse come in.

 

[darylz]

it's a simple verilog problem.

 

[fangjingyao]

Verilog Hdl Synthesis- a practical primer,by J.bhasker,is a good one book