module test(clk,out1,out2)
input clk;
output out1,out2;
reg out1,out2;
reg [1:0] next_state;
parameter [1:0] ONE = 2'b00,
TWO = 2'b01,
THREE = 2'b10,
FOUR = 2'b11;
paramter ON = 0,
OFF = 1;
always @ (next_state)
begin
out1 <= next_state[ON];
out2 <= next_state[OFF];
end
always @(posedge clk or posedge rst)
begin
if (posedge rst)
next_state <= ONE;
else
case (next_state)
ONE : next_sate <= TWO;
TWO : next_sate <= THREE;
THREE : next_sate <= FOUR;
FOUR : next_state <= ONE;
endcase
end