Verilog: Behavioral to Structural (gate level) Help

[gjivan72]

Hi,

I am trying to convert Verilog from behavioral to structural/gate level Verilog. I have been using Synopsys Design Compiler for the mos,t part but I have hit a problem with one of my designs. When ever I compile it the simulations dont match before synthesis. I was wondering if anyone knew another method. I have to feed the structural Verilog to another tool. I have been trying to see if XLINX ISE could do it but I have had no luck.

Thanks for any help,
-GJ

 

[cvc]

Hi,

I am trying to convert Verilog from behavioral to structural/gate level Verilog. I have been using Synopsys Design Compiler for the mos,t part but I have hit a problem with one of my designs. When ever I compile it the simulations dont match before synthesis. I was wondering if anyone knew another method. I have to feed the structural Verilog to another tool. I have been trying to see if XLINX ISE could do it but I have had no luck.

Thanks for any help,
-GJ

You may want to try out a good Linter prior to synthesis to see if it can detect code style issues out there. See: atrenta.com for expensive option, aldec.com (ALINT), realintent.com (Ascent, only in USA as of now)

If you can show the RTL code here, we maybe able to help better - or maybe your synthesis log file?

Good Luck
TeamCVC
www.cvcblr.com/blog

 

[gjivan72]

Thanks alot for your reply. It turns out I forgot to get rid of a few delays I had. They were not needed but were in some small modules I use previously. Thanks for the reply.