verilog basic question ???

[mohi@608]

i have a very simple ques on verilog basic

module abc(a,b,c);
input a;
input [3:0]b;
output [3:0]c;

module abc(input a,input [3:0] b, output [3:0] c);

which of the above coding style would be better ??

 

[mail4idle2]

It depends on person to person.
For me First style is comfortable.

 

[mohi@608]

well which is better from synthesis point of view ???
and i feel second is better as it is reducing the no. of lines of codes...

 

[Ow@i$]

number of lines are reduced in second... synthesis time will be same.

 

[mohi@608]

well the instantiation would be same for both the styles

abc k1(a,b,c);

 

[morris_mano]

For readability purpose, I like second one formatted as below:

module abc(
       input a,
       input [3:0] b, 
       output [3:0] c
 );

 

[dave_59]

The second style, also know as Verilog-2001 or ANSI-C style, is preferred. In this style, each port identifier is only declared once, not two or sometime three times for reg ports.

 

[subujohn]

The second one...Fewer lines of code...Does not effect simulation time/synthesis output.