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verilog basic question ???

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mohi@608

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i have a very simple ques on verilog basic
Code:
module abc(a,b,c);
input a;
input [3:0]b;
output [3:0]c;

Code:
module abc(input a,input [3:0] b, output [3:0] c);

which of the above coding style would be better ??
 

mail4idle2

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It depends on person to person.
For me First style is comfortable.
 

mohi@608

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well which is better from synthesis point of view ???
and i feel second is better as it is reducing the no. of lines of codes...
 

Ow@i$

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number of lines are reduced in second... synthesis time will be same.
 

mohi@608

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well the instantiation would be same for both the styles
Code:
abc k1(a,b,c);
 

morris_mano

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For readability purpose, I like second one formatted as below:
Code:
module abc(
       input a,
       input [3:0] b, 
       output [3:0] c
 );
 

dave_59

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The second style, also know as Verilog-2001 or ANSI-C style, is preferred. In this style, each port identifier is only declared once, not two or sometime three times for reg ports.
 

subujohn

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The second one...Fewer lines of code...Does not effect simulation time/synthesis output.
 

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