Nov 5, 2012 #1 M mohi@608 Member level 4 Joined Apr 4, 2012 Messages 69 Helped 1 Reputation 2 Reaction score 1 Trophy points 1,288 Activity points 1,719 i have a very simple ques on verilog basic Code: module abc(a,b,c); input a; input [3:0]b; output [3:0]c; Code: module abc(input a,input [3:0] b, output [3:0] c); which of the above coding style would be better ??
i have a very simple ques on verilog basic Code: module abc(a,b,c); input a; input [3:0]b; output [3:0]c; Code: module abc(input a,input [3:0] b, output [3:0] c); which of the above coding style would be better ??
Nov 5, 2012 #2 M mail4idle2 Full Member level 4 Joined Oct 20, 2012 Messages 200 Helped 20 Reputation 40 Reaction score 19 Trophy points 1,298 Activity points 2,173 It depends on person to person. For me First style is comfortable.
Nov 5, 2012 #3 M mohi@608 Member level 4 Joined Apr 4, 2012 Messages 69 Helped 1 Reputation 2 Reaction score 1 Trophy points 1,288 Activity points 1,719 well which is better from synthesis point of view ??? and i feel second is better as it is reducing the no. of lines of codes...
well which is better from synthesis point of view ??? and i feel second is better as it is reducing the no. of lines of codes...
Nov 5, 2012 #4 O Ow@i$ Advanced Member level 1 Joined Sep 18, 2012 Messages 413 Helped 78 Reputation 156 Reaction score 75 Trophy points 1,308 Location Pakistan Activity points 3,430 number of lines are reduced in second... synthesis time will be same.
Nov 5, 2012 #5 M mohi@608 Member level 4 Joined Apr 4, 2012 Messages 69 Helped 1 Reputation 2 Reaction score 1 Trophy points 1,288 Activity points 1,719 well the instantiation would be same for both the styles Code: abc k1(a,b,c);
Nov 9, 2012 #6 M morris_mano Full Member level 2 Joined Apr 9, 2012 Messages 137 Helped 39 Reputation 78 Reaction score 41 Trophy points 1,308 Location US Activity points 2,776 For readability purpose, I like second one formatted as below: Code: module abc( input a, input [3:0] b, output [3:0] c );
For readability purpose, I like second one formatted as below: Code: module abc( input a, input [3:0] b, output [3:0] c );
Nov 10, 2012 #7 D dave_59 Advanced Member level 3 Joined Dec 15, 2011 Messages 838 Helped 365 Reputation 734 Reaction score 360 Trophy points 1,353 Location Fremont, CA, USA Activity points 7,372 The second style, also know as Verilog-2001 or ANSI-C style, is preferred. In this style, each port identifier is only declared once, not two or sometime three times for reg ports.
The second style, also know as Verilog-2001 or ANSI-C style, is preferred. In this style, each port identifier is only declared once, not two or sometime three times for reg ports.
Nov 15, 2012 #8 S subujohn Newbie level 5 Joined Sep 21, 2012 Messages 8 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Location India Activity points 1,355 The second one...Fewer lines of code...Does not effect simulation time/synthesis output.