Verilog AMS sine wave generator

[pnpr]

I am trying to create a wrapper for my rxbb_lp module(which is VAMS netlist of my analog circuit) , the input of the wrapper is different from the input of the rxbb_lp module and I want to generate a signal(sine wave in my wrapper).
Is this the correct way to do it?
This is one of the ways I found to be suitable, but it does not seem to work.
Any suggestions would be of great help.

module rxbb_lp_wrapper


 (
   VDD1V8BB ,
   VSS1V8A ,
   VSS1V8BB ,
   VSS_SUB ,
   bbmux_lp_n_ai_amplitude ,
   bbmux_lp_n_ai_frequency ,
   bbmux_lp_n_ai_phase ,
   bbmux_lp_p_ai_amplitude ,
   bbmux_lp_p_ai_frequency ,
   bbmux_lp_p_ai_phase ,
   lp_n_ai_amplitude ,
   lp_n_ai_frequency ,
   lp_n_ai_phase ,
   lp_p_ai_amplitude ,
   lp_p_ai_frequency ,
   lp_p_ai_phase ,
   ibg_lp_untrim_50u_p_ai ,
   iptat_lp_untrim_50u_p_ai ,
   lp_en_i ,
   lp_noise_filter_en_i ,
   lp_test_sel_i ,
   trim_lp_fb_fc_i ,
   trim_lp_pass_fc_i ,
   vcm1_750m_ai ,
   vcm3_600m_ai ,
   lp1_n_amux_ao,
   lp1_p_amux_ao,
   lp2_n_amux_ao,
   lp2_p_amux_ao,
   lp_n_ao,
   lp_p_ao
   );
   
 input   VDD1V8BB;
 input   VSS1V8A;
 input   VSS1V8BB;
 input   VSS_SUB;
 input   bbmux_lp_n_ai_amplitude ;
 input   bbmux_lp_n_ai_frequency ;
 input   bbmux_lp_n_ai_phase ;
 input   bbmux_lp_p_ai_amplitude ;
 input   bbmux_lp_p_ai_frequency ;
 input   bbmux_lp_p_ai_phase ;
 input   lp_n_ai_amplitude ;
 input   lp_n_ai_frequency ;
 input   lp_n_ai_phase ;
 input   lp_p_ai_amplitude ;
 input   lp_p_ai_frequency ;
 input   lp_p_ai_phase ;
 input   [1:0] ibg_lp_untrim_50u_p_ai;
 input   [1:0] iptat_lp_untrim_50u_p_ai;
 input   lp_en_i;
 input   lp_noise_filter_en_i;
 input   lp_test_sel_i;
 input   [2:0] trim_lp_fb_fc_i;
 input   [3:0] trim_lp_pass_fc_i;
 input   vcm1_750m_ai;
 input   vcm3_600m_ai;
 output  lp1_n_amux_ao;
 output  lp1_p_amux_ao;
 output  lp2_n_amux_ao;
 output  lp2_p_amux_ao;
 output  lp_n_ao;
 output  lp_p_ao;
 
 wreal    VDD1V8BB;
 wreal    VSS1V8A;
 wreal    VSS1V8BB;
 wreal    VSS_SUB;
 wreal    bbmux_lp_n_ai_amplitude ;
 wreal    bbmux_lp_n_ai_frequency ;
 wreal    bbmux_lp_n_ai_phase ;
 wreal    bbmux_lp_p_ai_amplitude ;
 wreal    bbmux_lp_p_ai_frequency ;
 wreal    bbmux_lp_p_ai_phase ;
 wreal    lp_n_ai_amplitude ;
 wreal    lp_n_ai_frequency ;
 wreal    lp_n_ai_phase ;
 wreal    lp_p_ai_amplitude ;
 wreal    lp_p_ai_frequency ;
 wreal    lp_p_ai_phase ;
 wreal    ibg_lp_untrim_50u_p_ai[1:0];
wreal iptat_lp_untrim_50u_p_ai[1:0];
 wreal    lp_en_i;
 wreal    lp_noise_filter_en_i;
 wreal    lp_test_sel_i;
 wreal    trim_lp_fb_fc_i[2:0];
 wreal    trim_lp_pass_fc_i[3:0];
 wreal    vcm1_750m_ai;
 wreal    vcm3_600m_ai;
 wreal    lp1_n_amux_ao;
 wreal    lp1_p_amux_ao;
 wreal    lp2_n_amux_ao;
 wreal    lp2_p_amux_ao;
 wreal    lp_n_ao;
 wreal    lp_p_ao;
 electrical      bbmux_lp_n_ai;
 electrical      bbmux_lp_p_ai;
 electrical      lp_n_ai;
 electrical      lp_p_ai;
 
 real       offset = 2.5;
 
 
 
v(bbmux_lp_n_ai) <+ (offset + (bbmux_lp_n_ai_amplitude * sin(2*3.14159265358979323846*bbmux_lp_n_ai_frequency*$abstime)));
v(bbmux_lp_p_ai) <+ (offset + (bbmux_lp_p_ai_amplitude * sin(2*3.14159265358979323846*bbmux_lp_p_ai_frequency*$abstime)));
v(lp_n_ai) <+ (offset + (lp_n_ai_amplitude * sin(2*3.14159265358979323846*lp_n_ai_frequency*$abstime)));
v(lp_p_ai) <+ (offset + (lp_p_ai_amplitude * sin(2*3.14159265358979323846*lp_p_ai_frequency*$abstime)));
$bound_step(0.05/lp_p_ai_frequency);
 
 

 
 
   // Instantiate the analog netlist
 rxbb_lp rxbb_lp_inst(
   .VDD1V8BB(VDD1V8BB) ,
   .VSS1V8A(VSS1V8A) ,
   .VSS1V8BB(VSS1V8BB) ,
   .VSS_SUB(VSS_SUB) ,
   .bbmux_lp_n_ai(bbmux_lp_n_ai) ,
   .bbmux_lp_p_ai(bbmux_lp_p_ai) ,
.ibg_lp_untrim_50u_p_ai(ibg_lp_untrim_50u_p_ai) ,
.iptat_lp_untrim_50u_p_ai(iptat_lp_untrim_50u_p_ai) ,
   .lp_en_i(lp_en_i) ,
   .lp_n_ai(lp_n_ai) ,
.lp_noise_filter_en_i(lp_noise_filter_en_i) ,
   .lp_p_ai(lp_p_ai) ,
   .lp_test_sel_i(lp_test_sel_i) ,
.trim_lp_fb_fc_i(trim_lp_fb_fc_i) ,
.trim_lp_pass_fc_i(trim_lp_pass_fc_i) ,
   .vcm1_750m_ai(vcm1_750m_ai) ,
   .vcm3_600m_ai(vcm3_600m_ai) ,
   .lp1_n_amux_ao(lp1_n_amux_ao) ,
   .lp1_p_amux_ao(lp1_p_amux_ao) ,
   .lp2_n_amux_ao(lp2_n_amux_ao) ,
   .lp2_p_amux_ao(lp2_p_amux_ao) ,
   .lp_n_ao(lp_n_ao) ,
   .lp_p_ao(lp_p_ao)
 );
 

endmodule

Thank you