Verilog-a code for 8-3 priority encoder

[Engineer4ever]

Hi,

I am trying to design 64-6 priority encoder using verilog-a, so I started writing a code for 8-3 priority encoder for practicing as I am new to verilog-a. I tried the following code but there is a syntax error in "code=3'b000" line. How can I assign the the output of the encoder?

module priorityencoder (sel, code);
input [0:7] sel;
output [0:2] code;
electrical [0:7] sel;
electrical [0:2] code;

analog begin

if (sel[0]) begin
code=3'b000;
end 

else if (sel[1]) begin
.
.
.
.
.
endmodule

Thanks,