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Priority encoder for TDC in Verilog

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yeya

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I am implementing a TDC TDL on Artix 7 and I need an encoder to convert the thermometer code to binary code using an encoder. I did my research on several encoder approaches and ultimately chose to work with the priority encoder due to its effectiveness against bubble errors. it is a 7 bit 128 encoder. When I synthesized the TOP module (TDC+ENCODER), the encoder output of the submodule is changed (Q instead of bin) and the output is always 7 after the first pulse of the input signal. I don't understand the reason. (I put the diagram below) This is my encoder code (I tried to do pipelining) I have also posted the TDC code and the TOP module and the simulation for anyone interested in helping me. Thanks a lot.
 

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  • bh_simulation_encoder.PNG
    bh_simulation_encoder.PNG
    33.1 KB · Views: 88
  • encoder.txt
    2.2 KB · Views: 108
  • tdc.txt
    1.4 KB · Views: 98
  • testbench.txt
    786 bytes · Views: 99
  • top.txt
    1.2 KB · Views: 90

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